A CPU cannot execute an instruction simply by looking at a sequence of binary digits. It must know which bits represent the operation, which bits identify the data, and how the specified data should be accessed. The arrangement of these different parts inside a machine instruction is called the instruction format.
Instruction format provides a defined structure for machine instructions. When an instruction is fetched from memory, the control unit examines its fields and determines what operation has to be performed and where the required operands are located. Therefore, instruction format forms an important connection between the instruction stored in memory and the operation performed by the processor.
The exact format is not identical for every processor. Different CPU architectures use different instruction layouts depending on their design goals, register organization, addressing methods, and instruction set. However, the basic ideas of opcode, operands, and instruction fields are common when studying computer organization.
An instruction format is the arrangement of bits within a machine instruction. These bits are divided into different fields, and each field has a particular meaning.
The most important field is the opcode, which tells the processor what operation should be performed. Other fields may identify registers, memory locations, immediate data, or the addressing method used to locate an operand.
For example, an instruction that performs addition may need to specify the addition operation along with the registers containing the values. The processor obtains this information by interpreting the fields defined by its instruction format.
A machine instruction may contain several fields. The fields present depend on the instruction set architecture of the processor.
The opcode (operation code) identifies the operation that the CPU must perform. Examples of operations include addition, subtraction, data movement, comparison, logical operations, and program control.
During instruction decoding, the control unit interprets the opcode and generates the control signals required for the selected operation.
An operand field identifies the data involved in an operation or specifies where that data can be found. An operand may refer to a register, memory location, or an immediate value included within the instruction.
The number of operand fields depends on the instruction format. Some instructions contain no explicit operand, while others may contain one, two, or three explicit operands.
Some instruction formats contain one or more bits that indicate how the operand information should be interpreted. These bits are associated with the addressing mode.
For example, an operand field may represent a register number, a memory address, or a constant value. The addressing mode tells the CPU how to interpret that field.
Addressing modes are discussed separately in the next topic of this series.
A simplified instruction can be represented as follows:
+----------+------------------+-------------------+ | Opcode | Addressing Mode | Operand / Address | +----------+------------------+-------------------+
This is only a conceptual representation. Actual processors may use completely different layouts. Some instructions may contain several register fields, while others may contain immediate data or displacement values.
The important idea is that an instruction contains encoded information that allows the CPU to determine what operation to perform and what information is required to perform it.
In basic computer organization studies, instructions are often classified according to the number of explicit operand addresses they contain. On this basis, four commonly discussed formats are:
These formats are useful for understanding how different CPU organizations represent arithmetic expressions and where operands and results are stored.
A zero-address instruction does not contain an explicit operand address. It is normally associated with a stack-based organization.
In a stack-based system, operands are placed on the stack before an arithmetic operation is performed. The instruction itself does not need to specify where the operands are located because the processor obtains them from the top of the stack.
Suppose we want to calculate:
10 + 20
A simplified sequence could be:
PUSH 10 PUSH 20 ADD
Before ADD is executed, the values 10 and 20 are already available on the stack. The ADD instruction takes the required values from the stack, performs the addition, and places the result back on the stack.
The important point is that ADD contains no explicit operand address. The stack determines the operands implicitly.
A one-address instruction contains one explicit operand address. In the traditional accumulator-based organization, the accumulator acts as an implied operand.
The accumulator also commonly receives the result of the operation. Therefore, only one operand needs to be specified explicitly in the instruction.
ADD X
A simplified interpretation is:
AC ← AC + M[X]
Here:
If the accumulator contains 15 and memory location X contains 25, execution of the instruction produces:
AC = 15 + 25 AC = 40
The accumulator is implicit, so its address does not have to be written in the instruction.
A two-address instruction explicitly identifies two operands. In many two-address instruction sets, one operand is used both as a source and as the destination for the result.
ADD R1, R2
A common interpretation is:
R1 ← R1 + R2
Suppose:
R1 = 30 R2 = 12
After execution:
R1 = 42 R2 = 12
The original value of R1 is replaced by the result. R2 remains unchanged.
This arrangement allows the processor to specify two operands without requiring a separate destination field, which can reduce the number of bits needed for the instruction compared with a three-address representation.
A three-address instruction provides separate fields for two source operands and a destination operand. This allows the processor to preserve both input values while storing the result somewhere else.
ADD R3, R1, R2
A common interpretation is:
R3 ← R1 + R2
Suppose:
R1 = 30 R2 = 12
After execution:
R3 = 42 R1 = 30 R2 = 12
Unlike the two-address example, neither R1 nor R2 is overwritten. The result is placed in the separately specified destination register R3.
| Instruction Type | Explicit Addresses | Typical Organization | Example | Result Handling |
|---|---|---|---|---|
| Zero Address | 0 | Stack-based | ADD | Operands are obtained implicitly from the stack |
| One Address | 1 | Accumulator-based | ADD X | Accumulator is normally an implied operand and destination |
| Two Address | 2 | Register/memory based | ADD R1, R2 | One specified operand commonly acts as destination |
| Three Address | 3 | Register-based designs | ADD R3, R1, R2 | Separate destination can preserve both source operands |
The difference between instruction formats becomes easier to understand when the same arithmetic expression is represented using different organizations.
Consider:
X = A + B
ADD X, A, B
This directly expresses the destination and both source operands:
X ← A + B
One possible representation is:
MOV X, A ADD X, B
The first instruction places A into X. The second instruction adds B to X.
Using an accumulator, the same operation can be represented as:
LOAD A ADD B STORE X
Here the accumulator holds the intermediate result.
A stack-oriented representation could be:
PUSH A PUSH B ADD POP X
The operands are supplied through the stack rather than explicit addresses in the ADD instruction.
These examples demonstrate an important principle: the same computation can require different instruction sequences depending on how the processor represents operands and results.
The number and size of instruction fields influence the overall length of a machine instruction. An instruction containing an opcode, several register identifiers, an addressing mode, and an immediate value may require more bits than a simple instruction containing only an opcode.
Instruction length can be fixed or variable, depending on the processor architecture.
In a fixed-length instruction set, instructions generally occupy the same number of bits. This makes instruction fetching and decoding more predictable and can simplify certain aspects of processor design.
In a variable-length instruction set, different instructions may occupy different numbers of bytes. The length can depend on the operation and the fields required by that particular instruction.
The choice between fixed and variable instruction lengths is an architectural design decision involving factors such as code density, decoding complexity, and processor implementation.
The number of bits allocated to the opcode places a limit on how many distinct operation codes can be represented directly.
For example, if an instruction format reserves 6 bits for the opcode, the number of possible binary opcode combinations is:
2⁶ = 64
Therefore, up to 64 different opcode patterns can be represented by that field, although an actual instruction set may use fewer patterns or use some combinations for other purposes.
Similarly, if more bits are assigned to operand addresses, fewer bits remain available for other fields unless the total instruction length is increased.
Instruction format design involves balancing several requirements. A processor needs enough information in an instruction to identify the operation and its operands, but increasing the number of fields can increase instruction size and decoding complexity.
For example, a three-address instruction can express an operation using two source operands and a separate destination in one instruction. A simpler format may require additional instructions because some operands or destinations are implied.
Therefore, there is no single instruction format that is ideal for every processor. The format is designed according to the goals of the instruction set architecture and the organization of the CPU.
These two terms are related but should not be confused.
| Concept | Meaning |
|---|---|
| Instruction Set | The collection of operations that a processor understands and can execute. |
| Instruction Format | The arrangement of bits used to represent those instructions. |
For example, an instruction set may contain operations such as ADD, SUB, LOAD, STORE, and JUMP. The instruction format defines how the opcode and other information required by those operations are encoded.
Instruction format and addressing modes work together when the CPU determines where an operand should come from.
Consider a simplified instruction:
LOAD R1, 25
Depending on the architecture, the value 25 could represent an immediate constant, a memory address, or another form of operand information. The addressing mode tells the processor how to interpret that field.
Therefore, understanding instruction formats provides the foundation for understanding addressing modes. In the next topic, different addressing techniques are examined in detail.
Instruction format explains how a processor's machine instructions are organized internally. Instead of treating an instruction as an uninterpreted collection of binary digits, the CPU divides it into meaningful fields such as the opcode, operand information, and, where required, addressing-mode information.
The zero-address, one-address, two-address, and three-address models provide a useful way to understand how different processor organizations represent operands and results. A stack-based design can obtain operands implicitly, an accumulator-based design can use an implied accumulator, while multi-address formats can explicitly identify source and destination locations.
The actual instruction formats used by modern processors are more detailed than these simplified academic models, but the underlying principle remains the same: the instruction must contain enough encoded information for the processor to determine the required operation and obtain the information needed to execute it.