A computer does not work with the processor and main memory alone. It must communicate with devices outside the CPU and memory system, including keyboards, displays, storage devices, printers, network interfaces, sensors, and many other peripherals. The part of computer organization that explains how this communication is managed is called Input Output (I/O) Organization.
I/O organization is concerned with much more than simply sending data into and out of a computer. It deals with the mechanisms used to identify devices, transfer data, communicate device status, handle control information, and coordinate devices that operate at very different speeds from the processor. A well-designed I/O system allows the CPU to communicate with peripherals without unnecessarily wasting processing time.
The basic challenge is that a processor can execute instructions extremely quickly, whereas an external device may take considerably longer to produce or consume data. For this reason, computer systems use different I/O techniques depending on the type and volume of data being transferred.
Input Output Organization refers to the hardware and control mechanisms used by a computer to exchange information between the CPU, memory, and peripheral devices.
The CPU normally works with data in registers and memory, while peripheral devices have their own operating characteristics. An I/O system provides the necessary connection between these two environments.
For example, when a key is pressed on a keyboard, the computer must detect that an event has occurred, obtain the corresponding data, and make that data available to software. Similarly, when a program requests a file from a storage device, the system must coordinate the transfer of that information into memory.
Therefore, I/O organization provides the communication mechanism through which the processor can interact with devices that are not part of the CPU's internal processing circuitry.
Different hardware components do not operate at the same speed or in the same manner. The CPU may execute instructions in extremely short time intervals, while an external device may need much longer to respond. A communication mechanism is therefore required to prevent the processor from being unnecessarily tied to slow device operations.
Another issue is that peripheral devices do not all transfer information in the same way. A keyboard may generate only a few characters at a time, whereas a storage device may transfer thousands or millions of bytes during a single operation.
I/O organization addresses these differences by providing mechanisms for:
Communication between the CPU and a peripheral device generally involves more than the physical device itself. An I/O interface or controller is commonly placed between the system bus and the peripheral so that differences in timing, data format, and control requirements can be handled appropriately.
An I/O device is a peripheral that exchanges information with the computer. Examples include keyboards, mice, monitors, printers, disks, network adapters, and sensors.
The device is responsible for performing its specific physical function, such as detecting a key press, displaying an image, or reading information from storage.
An I/O controller provides the communication mechanism between the system and a peripheral device. It manages device-specific operations and exposes information that the CPU or operating system can access.
Depending on the hardware design, an I/O controller may contain registers for data, status information, and control commands.
A data register temporarily holds information being transferred between the computer and an I/O device. For example, a keyboard controller may place the code representing a pressed key into a data register so that the processor can obtain it.
A status register contains information about the current condition of a device. It may indicate whether data is available, whether a transfer has completed, or whether an error has occurred.
A control register is used to provide commands or configuration information to an I/O controller. The exact meaning of individual control bits depends on the particular device and hardware design.
The processor generally communicates with an I/O device by accessing registers associated with the device or its controller. A typical interaction can be viewed as a sequence of operations rather than as direct communication between the CPU and the physical peripheral.
CPU | | Read / Write / Control information | v I/O Controller | |------------------| | | Data Register Status/Control Registers | v I/O Device
For example, suppose a processor wants to read data from a device. It may first examine a status register to determine whether data is available. Once the device is ready, the processor can obtain the data through the appropriate data register.
The exact implementation differs between systems, but the general idea remains the same: the I/O controller provides a controlled interface between the processor and the peripheral.
The three fundamental approaches commonly discussed in Computer Organization are Programmed I/O, Interrupt-Driven I/O, and Direct Memory Access (DMA).
The main difference between these approaches is the amount of responsibility assigned to the CPU during a data transfer.
In Programmed I/O, the processor controls the I/O operation by executing instructions that check the device and transfer the data. The CPU typically examines a status condition repeatedly until the device becomes ready.
This repeated checking is known as polling. While the CPU is polling, it is actively spending processing time on the I/O operation.
CPU
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| Check keyboard status
v
I/O Controller
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| Is data available?
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+---- No ----> CPU checks again
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+---- Yes ---> Read data register
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v
Character
Suppose a program is waiting for a keyboard character. The processor can repeatedly read the keyboard's status information until the controller reports that a character is available. It then reads the character from the appropriate register.
The technique is straightforward, but the processor may spend considerable time checking a device that is not yet ready.
The defining feature of programmed I/O is that the CPU actively manages the transfer and checks the device condition itself.
Interrupt-driven I/O changes the way the processor waits for a device. Instead of repeatedly checking the device, the CPU can continue executing other instructions. When the device requires attention or becomes ready, it generates an interrupt.
The processor responds to the interrupt by temporarily suspending its current execution and transferring control to an appropriate interrupt-handling routine. After the required I/O work is completed, normal execution can continue.
CPU is executing another program
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v
Keyboard receives a key press
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v
Keyboard Controller generates interrupt
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v
CPU detects interrupt
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v
CPU executes interrupt-handling routine
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v
Character is obtained
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v
CPU resumes previous execution
The major benefit is that the CPU does not need to continuously ask whether the device is ready. It can perform useful work until an interrupt indicates that attention is required.
Interrupt-driven I/O is particularly useful for devices whose events occur irregularly, such as keyboards, mice, communication interfaces, and many other peripherals.
When large amounts of data have to be transferred, even interrupt-driven I/O can involve substantial CPU overhead if the processor must participate in each individual data movement. Direct Memory Access (DMA) provides a more efficient approach.
With DMA, a dedicated hardware component called a DMA controller can manage a data transfer between an I/O device and main memory without requiring the CPU to execute an instruction for every transferred item.
The CPU normally initializes the DMA operation by providing information such as:
After initialization, the DMA controller manages the transfer. When the operation finishes, the controller can notify the processor, commonly through an interrupt.
Initial Setup
CPU ------------------------------> DMA Controller
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v
I/O Device
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v
Main Memory
After transfer is completed
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v
Interrupt CPU
The important point is that the CPU does not have to execute a separate data-transfer instruction for every individual byte or word. This makes DMA especially useful for high-volume transfers involving devices such as storage controllers and network interfaces.
| Feature | Programmed I/O | Interrupt-Driven I/O | DMA |
|---|---|---|---|
| CPU involvement | High | Moderate | Low during bulk transfer |
| Device notification | CPU repeatedly checks status | Device generates interrupt | DMA controller manages transfer |
| Large data transfers | Less efficient | Better than polling, but CPU still participates | Highly suitable |
| CPU available for other work | Limited while polling | Generally yes | Yes during the main transfer |
| Additional hardware | Minimal | Interrupt hardware required | DMA hardware/controller required |
Polling and interrupts represent two different ways of determining when a device needs attention.
With polling, the processor asks the device whether it is ready. The processor controls when the status is checked.
CPU → Are you ready? CPU → Are you ready? CPU → Are you ready? CPU → Are you ready? Device → Yes CPU → Transfer data
Polling is simple to implement, but frequent status checks can consume CPU time.
With interrupts, the processor does not have to continuously ask the device. Instead, the device or controller signals the CPU when attention is required.
CPU → Continue normal execution Device → Interrupt! CPU → Handle I/O event CPU → Resume previous execution
The choice between polling and interrupts depends on the device, workload, timing requirements, and system architecture.
Computer architectures can use different methods for addressing I/O devices. Two commonly discussed techniques are memory-mapped I/O and isolated I/O.
In memory-mapped I/O, I/O device registers are assigned addresses within the processor's normal memory address space. The processor can use ordinary memory-access instructions to communicate with those registers.
For example, a particular address may correspond to a device status register rather than physical RAM. Reading from that address causes the processor to obtain information from the device interface.
In isolated I/O, I/O devices have a separate address space from main memory. Architectures supporting this approach provide specific instructions or mechanisms for performing I/O operations.
| Feature | Memory-Mapped I/O | Isolated I/O |
|---|---|---|
| Address space | I/O registers share the memory address space | I/O has a separate address space |
| Access mechanism | Memory-access instructions can be used | Dedicated I/O instructions may be used |
| Memory address usage | Some addresses are assigned to I/O devices | Memory addresses remain separate from I/O addresses |
Consider a storage device that needs to place a large block of data into main memory. The exact implementation depends on the system, but the conceptual sequence can be understood as follows.
Step 1: CPU requests a data transfer. Step 2: The I/O controller prepares the device. Step 3: The transfer mechanism determines the destination memory address and amount of data. Step 4: Data moves from the device toward main memory. Step 5: The transfer is completed. Step 6: The CPU is notified that the requested operation has completed.
For a large transfer, DMA can perform the bulk movement without requiring the CPU to manage each individual data item.
An I/O controller is important because peripheral devices cannot always communicate with the processor using the same timing and control conventions used internally by the CPU.
A controller can provide registers representing different aspects of the device. A simplified controller may contain:
| Register | Purpose |
|---|---|
| Data Register | Holds data being transferred to or from the device. |
| Status Register | Indicates conditions such as ready, busy, completed, or error. |
| Control Register | Receives commands or configuration information. |
The actual number and meaning of registers vary according to the device and hardware architecture. The important concept is that the controller provides a structured interface through which the computer can operate the peripheral.
Suppose a system needs to transfer a large block of information from a storage device into memory. If the CPU had to execute a separate transfer operation for every small portion of the data, processor time would be consumed by repetitive movement rather than application processing.
DMA changes this arrangement. The CPU establishes the transfer parameters, and the DMA mechanism performs the bulk transfer. Once the operation has completed, the CPU can be informed that the data is ready.
This separation is particularly valuable when the transfer involves a large amount of data or when the CPU has other useful work to perform at the same time.
Interrupts are closely related to I/O organization because they provide a way for hardware to request processor attention. An I/O controller may generate an interrupt when an operation has completed, when data has arrived, or when an error requires attention.
The CPU's response involves saving enough information to resume its current execution, transferring control to an appropriate interrupt-handling routine, servicing the event, and eventually returning to the interrupted program.
Therefore, interrupt-driven I/O and the interrupt mechanism studied in Computer Organization are directly connected. I/O devices are one of the major sources of hardware interrupts in computer systems.
The appropriate I/O mechanism depends on the characteristics of the workload rather than on a single universal rule.
| Situation | Suitable Approach | Reason |
|---|---|---|
| Simple device with small amounts of data | Programmed I/O | The simplicity of direct CPU control may be sufficient. |
| Device produces occasional events | Interrupt-driven I/O | The CPU does not need to continuously poll the device. |
| Large block of data must be transferred | DMA | The bulk transfer can occur with limited CPU involvement. |
These approaches should not be viewed as completely unrelated alternatives. A real computer system may use different mechanisms for different devices and operations.
| Common Mistake | Correct Understanding |
|---|---|
| Thinking that interrupt-driven I/O means the CPU performs no I/O work. | The CPU still handles the interrupt and performs the required processing; it simply does not need to continuously poll the device. |
| Assuming DMA completely removes the CPU from the I/O operation. | The CPU normally initializes the DMA transfer and may receive an interrupt after completion. |
| Confusing polling with interrupts. | Polling means the CPU checks device status; an interrupt allows the device/controller to request CPU attention. |
| Thinking every peripheral transfers data at the same speed. | Different devices have different data rates, timing requirements, and transfer characteristics. |
| Assuming an I/O device communicates directly with CPU registers in every system. | I/O controllers and interfaces commonly provide the hardware boundary between the processor and peripheral. |
Input Output Organization describes the hardware mechanisms and techniques used to exchange information between the CPU, memory, and peripheral devices.
Programmed I/O is an I/O technique in which the CPU directly controls the transfer and typically checks the device status through polling.
Polling is a technique in which the CPU repeatedly checks the status of an I/O device to determine whether the device is ready for an operation.
Interrupt-driven I/O allows the CPU to perform other work while a device is not ready. The device or its controller generates an interrupt when CPU attention is required.
Direct Memory Access is a technique that allows a DMA controller or equivalent hardware to transfer data between an I/O device and main memory with limited CPU involvement during the actual transfer.
DMA is useful for large or frequent data transfers because it reduces the number of CPU operations required to move the data.
An I/O controller is hardware that manages communication between a peripheral device and the computer system. It may contain data, status, and control registers.
In polling, the CPU repeatedly asks whether a device requires attention. With interrupts, the device or controller signals the CPU when attention is required.
Memory-mapped I/O assigns I/O device registers addresses within the processor's memory address space, allowing normal memory-access mechanisms to be used for communication with those registers.
DMA is generally well suited to large data transfers because the CPU does not need to manage every individual data movement.
Input Output Organization explains how a computer system exchanges information with devices that exist outside the processor and main memory. Because peripheral devices differ significantly in speed, timing, and operating behavior, the computer requires dedicated mechanisms for controlling and coordinating these interactions.
An I/O controller provides an interface through which the processor can access device data, status information, and control operations. Data transfer can be organized through programmed I/O, interrupt-driven I/O, or Direct Memory Access. Programmed I/O gives the CPU direct responsibility for checking and managing the device, interrupt-driven I/O allows the device to notify the processor when attention is required, and DMA moves large amounts of data with much less processor involvement during the transfer itself.
Understanding I/O organization is important because it connects several major Computer Organization concepts, including buses, registers, memory, interrupts, and CPU operation. It also provides the foundation for understanding how operating systems communicate with hardware devices.